This invention is in the field of computer systems, and particularly pertains to the testing of computer restart, retry and recovery mechanisms by the purposeful injection of errors into a computer system in order to provoke and evaluate a restart, retry or recovery mechanism.
In the past art of error injection, errors were injected by probing pins or circuit paths in order to force connected circuitry to certain states indicating the occurrence of errors. With miniaturization and integration of circuit functions resulting in a manifold increase of functionality on a decreasing physical base, specific circuit points of interest are usually not available at accessible locations. Packaging and miniaturization make the probing of specific points internal to circuitry impractical. Further, the nature of circuit technology currently in vogue is not compatible with "OR dotting" of an error signal into a circuit.
Further, the known modes of error injection are unsuitable for realistically evaluating computer error response. The prior art of error injection is based primarily upon error initiation which occurs without regard to, or as the result of, circuit operation. In this regard, error injection may be synchronized with circuit operations in the sense that the error injection mechanism responds to a clock which also drives the circuit that will receive the error. However, the mechanism initiates the error with total disregard for circuit events Therefore, the error is triggered in an arbitrary manner, without considering the state of the circuit.
Therefore, there is a manifest need for an error injection mechanism in a computer system which can simulate computer malfunction by injecting errors by a means which is compatible with circuit fabrication technology, and in a mode which is influenced by machine operation.